公开(公告)号：US09569613B2

公开(公告)日：2017-02-14

申请号：US14581871

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Koichi Yamada ,  Palanivelrajan Shanmugavelayutham ,  Sravani Konda

IPC: G06F21/00 ,  G06F21/54 ,  G06F9/44

CPC classification number: G06F21/54 ,  G06F8/30 ,  G06F8/52 ,  G06F9/4552

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.

Abstract translation: 各种实施例通常涉及一种装置，方法和其他技术，以从存储在重定位表，链接表或二者中的信息确定分支指令的有效目标地址，重定位表和与二进制文件相关联的链接表 并将有效目标地址存储在存储器中的表中，该有效目标地址用于验证二进制文件的例程的翻译部分的目标地址。

公开(公告)号：US10268819B2

公开(公告)日：2019-04-23

申请号：US15430652

申请日：2017-02-13

Applicant: INTEL CORPORATION

Inventor： Koichi Yamada ,  Palanivelrajan Shanmugavelayutham ,  Sravani Konda

IPC: G06F21/00 ,  G06F21/54 ,  G06F8/30 ,  G06F8/52 ,  G06F9/455

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.