Invention Grant
- Patent Title: Methods and apparatus for efficient linear combiner
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Application No.: US15645647Application Date: 2017-07-10
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Publication No.: US10277202B2Publication Date: 2019-04-30
- Inventor: Jaiganesh Balakrishnan , Sthanunathan Ramakrishnan , Pooja Sundar , Sashidharan Venkatraman
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Priority: IN201641024045 20160714
- Main IPC: H03H17/02
- IPC: H03H17/02 ; H03H17/00 ; G06F5/01 ; G06F7/544 ; H03H17/06 ; H03M1/06 ; H03M1/12

Abstract:
In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
Public/Granted literature
- US20180019732A1 METHODS AND APPARATUS FOR EFFICIENT LINEAR COMBINER Public/Granted day:2018-01-18
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