Invention Grant
- Patent Title: Technologies for translation cache management in binary translation systems
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Application No.: US15274624Application Date: 2016-09-23
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Publication No.: US10282182B2Publication Date: 2019-05-07
- Inventor: Paul Caprioli , Jeffrey J. Cook
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F8/52
- IPC: G06F8/52 ; G06F11/34 ; G06F12/02 ; G06F9/455 ; G06F9/30

Abstract:
Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a translation cache. The cost-benefit metric is indicative of translation cost and performance benefit associated with the translated code block. The translation cost may be determined by measuring translation time of the translated code block. The cost-benefit metric may be calculated using a weighted cost-benefit function based on an expected workload of the computing device. In response to determining to free space in the translation cache, the computing device determines whether to discard each translated code block as a function of the cost-benefit metric. In response to determining to free space in the translation cache, the computing device may increment an iteration count and skip each translated code block if the iteration count modulo the corresponding cost-benefit metric is non-zero. Other embodiments are described and claimed.
Public/Granted literature
- US20180088921A1 TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION SYSTEMS Public/Granted day:2018-03-29
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