Invention Grant
- Patent Title: Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit
-
Application No.: US15845930Application Date: 2017-12-18
-
Publication No.: US10283588B2Publication Date: 2019-05-07
- Inventor: Emmanuel Perrin
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Seed IP Law Group LLP
- Priority: FR1554853 20150529
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/12 ; H01L29/06 ; H01L29/66 ; H01L21/762 ; H01L21/8238

Abstract:
An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.
Public/Granted literature
Information query
IPC分类: