Invention Grant
- Patent Title: Structure and method to achieve large strain in NS without addition of stack-generated defects
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Application No.: US15086015Application Date: 2016-03-30
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Publication No.: US10283638B2Publication Date: 2019-05-07
- Inventor: Jorge A. Kittl , Ganesh Hegde , Robert C. Bowen , Mark S. Rodder
- Applicant: Jorge A. Kittl , Ganesh Hegde , Robert C. Bowen , Mark S. Rodder
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Rennissance IP Law Group LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L29/06 ; H01L29/66

Abstract:
A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.
Public/Granted literature
- US20170040455A1 STRUCTURE AND METHOD TO ACHIEVE LARGE STRAIN IN NS WITHOUT ADDITION OF STACK-GENERATED DEFECTS Public/Granted day:2017-02-09
Information query
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