Invention Grant
- Patent Title: Circuit structures with vertically spaced transistors and fabrication methods
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Application No.: US15160623Application Date: 2016-05-20
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Publication No.: US10290654B2Publication Date: 2019-05-14
- Inventor: Hui Zang , Manfred Eller , Min-hwa Chi
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Francois Pagette
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L27/092 ; H01L29/49 ; H01L21/8238 ; H01L21/84 ; H01L27/11 ; H01L21/8234

Abstract:
Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor.
Public/Granted literature
- US20170338247A1 CIRCUIT STRUCTURES WITH VERTICALLY SPACED TRANSISTORS AND FABRICATION METHODS Public/Granted day:2017-11-23
Information query
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