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    Semiconductor memory devices having an undercut source/drain region
    3.
    发明授权
    Semiconductor memory devices having an undercut source/drain region 有权

    公开(公告)号：US10157927B2

    公开(公告)日：2018-12-18

    申请号：US15404754

    申请日：2017-01-12

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Manfred Eller

    IPC分类号： H01L27/088 ,  H01L27/108 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78

    摘要： A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

    FINFET circuit structures with vertically spaced transistors and fabrication methods
    4.
    发明授权
    FINFET circuit structures with vertically spaced transistors and fabrication methods 有权

    公开(公告)号：US10147802B2

    公开(公告)日：2018-12-04

    申请号：US15160591

    申请日：2016-05-20

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/12 ,  H01L27/02

    摘要： Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

    SOI-based semiconductor device with dynamic threshold voltage
    6.
    发明授权
    SOI-based semiconductor device with dynamic threshold voltage 有权

    公开(公告)号：US09601512B2

    公开(公告)日：2017-03-21

    申请号：US14801519

    申请日：2015-07-16

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Manfred Eller

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

    CPC分类号： H01L27/1203 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78648

    摘要： A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure. Operating the device includes applying a variable voltage at the contact for the inner well, a threshold voltage for the first transistor being altered by the variable voltage. The inner well and gate may be exposed and contacts created therefor together.

    Methods of forming doped transition regions of transistor structures
    7.
    发明授权
    Methods of forming doped transition regions of transistor structures 有权
    形成晶体管结构的掺杂过渡区的方法

    公开(公告)号：US09484417B1

    公开(公告)日：2016-11-01

    申请号：US14805907

    申请日：2015-07-22

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Xusheng Wu ,  Manfred Eller

    IPC分类号： H01L29/167 ,  H01L29/161 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

    CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1218 ,  H01L29/165 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684

    摘要： Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region.

    摘要翻译： 本文提供了形成晶体管结构的掺杂过渡区的方法。 所述方法包括例如：在晶体管结构的源极/漏极区域上提供包括掺杂剂的第一半导体材料; 在所述第一半导体材料上提供包括所述掺杂剂的第二半导体材料，其中所述第二半导体材料不同于所述第一半导体材料; 并且其中提供第二半导体材料的温度足以将掺杂剂从第一半导体材料通过源/漏区扩散到晶体管结构的沟道区的一部分中。 来自第一半导体材料的掺杂剂扩散的沟道区的部分形成掺杂的过渡区。

    METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES
    8.
    发明申请
    METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLICATIONS AND THE RESULTING DEVICE STRUCTURES 有权
    在CMOS应用中形成晶体管的方法和结构化器件结构

    公开(公告)号：US20140367787A1

    公开(公告)日：2014-12-18

    申请号：US13918536

    申请日：2013-06-14

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

    IPC分类号： H01L27/092 ,  H01L21/8234

    CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

    摘要： A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

    摘要翻译： 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

    Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures
    9.
    发明授权
    Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures 有权

    公开(公告)号：US10529724B2

    公开(公告)日：2020-01-07

    申请号：US16056660

    申请日：2018-08-07

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

    IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

    摘要： A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

    Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts
    10.
    发明授权
    Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts 有权

    公开(公告)号：US10083971B1

    公开(公告)日：2018-09-25

    申请号：US15654190

    申请日：2017-07-19

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

    IPC分类号： H01L27/11 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/1104 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

    摘要： A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.