Invention Grant
- Patent Title: Hierarchical fail bit counting circuit in memory device
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Application No.: US15669739Application Date: 2017-08-04
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Publication No.: US10297337B2Publication Date: 2019-05-21
- Inventor: Wanfang Tsai , Hung-Szu Lin , Yi-Fang Chen
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C29/44
- IPC: G11C29/44 ; H03K23/40

Abstract:
Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.
Public/Granted literature
- US20190043603A1 Hierarchical Fail Bit Counting Circuit In Memory Device Public/Granted day:2019-02-07
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