Hierarchical fail bit counting circuit in memory device

    公开(公告)号:US10297337B2

    公开(公告)日:2019-05-21

    申请号:US15669739

    申请日:2017-08-04

    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

    Hierarchical Fail Bit Counting Circuit In Memory Device

    公开(公告)号:US20190043603A1

    公开(公告)日:2019-02-07

    申请号:US15669739

    申请日:2017-08-04

    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

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