Invention Grant
- Patent Title: Wafer alignment method and system
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Application No.: US15848127Application Date: 2017-12-20
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Publication No.: US10300554B2Publication Date: 2019-05-28
- Inventor: Peter Mains , Anmiv S. Prabhu , Richard Capella , Kevan Samiee
- Applicant: Illumina, Inc.
- Applicant Address: US CA San Diego
- Assignee: ILLUMINA, INC.
- Current Assignee: ILLUMINA, INC.
- Current Assignee Address: US CA San Diego
- Agency: Illumina, Inc.
- Main IPC: B23K26/00
- IPC: B23K26/00 ; B29C65/00 ; B23K26/02 ; B23K26/21 ; B29C65/78 ; B23K26/03 ; B23K26/08 ; B23K26/324 ; B23K26/38 ; B23K26/402 ; B23K103/00 ; B23K101/40

Abstract:
Wafers are aligned with one another by reference to features formed on or in each wafer. Notches are formed in each wafer, including a pivot-notch that allows for two-point contact, and a stop-notch that provides for single-point contact. A bias-notch is formed for pressing the wafers into engagement with the two-contact element when it is in the pivot-notch and with the single-contact element when it is in the stop-notch. The wafers may be bonded to one another to maintain the alignment of the referenced features.
Public/Granted literature
- US20180214977A1 WAFER ALIGNMENT METHOD AND SYSTEM Public/Granted day:2018-08-02
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