- 专利标题: Wiring layer and manufacturing method therefor
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申请号: US15708714申请日: 2017-09-19
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公开(公告)号: US10304864B2公开(公告)日: 2019-05-28
- 发明人: Yutaka Okazaki , Tomoaki Moriwaka , Shinya Sasagawa , Takashi Ohtsuki
- 申请人: Semiconductor Energy Laboratory Co., Ltd.
- 申请人地址: JP
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: JP
- 代理机构: Husch Blackwell LLP
- 优先权: JP2014-202820 20141001
- 主分类号: H01L27/12
- IPC分类号: H01L27/12 ; H01L29/66 ; H01L29/786 ; H01L21/768 ; H01L23/532
摘要:
To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
公开/授权文献
- US20180006061A1 Wiring Layer and Manufacturing Method Therefor 公开/授权日:2018-01-04
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