Invention Grant
- Patent Title: Dynamic scan chain reconfiguration in an integrated circuit
-
Application No.: US15589644Application Date: 2017-05-08
-
Publication No.: US10317464B2Publication Date: 2019-06-11
- Inventor: Partho Tapan Chaudhuri
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Robert M. Brush
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177 ; G01R31/3185 ; G01R31/3187 ; G06F11/267 ; G06F11/27

Abstract:
An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.
Public/Granted literature
- US20180321306A1 DYNAMIC SCAN CHAIN RECONFIGURATION IN AN INTEGRATED CIRCUIT Public/Granted day:2018-11-08
Information query