- Patent Title: Enabling error status and reporting in a machine check architecture
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Application No.: US15168999Application Date: 2016-05-31
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Publication No.: US10318368B2Publication Date: 2019-06-11
- Inventor: Ashok Raj , Theodros Yigzaw
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/07

Abstract:
In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.
Public/Granted literature
- US20170344414A1 ENABLING ERROR STATUS AND REPORTING IN A MACHINE CHECK ARCHITECTURE Public/Granted day:2017-11-30
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