- 专利标题: Techniques for statistical frequency enhancement of statically timed designs
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申请号: US15414739申请日: 2017-01-25
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公开(公告)号: US10318676B2公开(公告)日: 2019-06-11
- 发明人: Alfred Yeung , Subbayyan Venkatsan , Hamid Partovi , Vamsi Srikantam
- 申请人: Ampere Computing LLC
- 申请人地址: US CA Santa Clara
- 专利权人: AMPERE COMPUTING LLC
- 当前专利权人: AMPERE COMPUTING LLC
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Alston & Bird LLP
- 主分类号: G06F9/455
- IPC分类号: G06F9/455 ; G06F17/50
摘要:
Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.
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