公开(公告)号：US11049854B1

公开(公告)日：2021-06-29

申请号：US15860748

申请日：2018-01-03

申请人： Ampere Computing LLC

发明人： Ronen Cohen ,  Alfred Yeung ,  Ojas Dharia

IPC分类号： H01L27/02 ,  H01L23/535 ,  H01L23/522 ,  H01L49/02 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

摘要： A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.

公开(公告)号：US10145868B2

公开(公告)日：2018-12-04

申请号：US15068737

申请日：2016-03-14

申请人： Ampere Computing LLC

发明人： Yan Chong ,  Luca Ravezzi ,  Alfred Yeung ,  Hamid Partovi

IPC分类号： G01R19/00 ,  G01R19/165 ,  G01R17/02

摘要： A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.

公开(公告)号：US10318676B2

公开(公告)日：2019-06-11

申请号：US15414739

申请日：2017-01-25

申请人： Ampere Computing LLC

发明人： Alfred Yeung ,  Subbayyan Venkatsan ,  Hamid Partovi ,  Vamsi Srikantam

IPC分类号： G06F9/455 ,  G06F17/50

摘要： Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

公开(公告)号：US20180166126A1

公开(公告)日：2018-06-14

申请号：US15372581

申请日：2016-12-08

申请人： Ampere Computing LLC

发明人： Russell Homer ,  Abhiram Saligram Chandrashekar ,  Alfred Yeung

IPC分类号： G11C11/419 ,  G11C11/418 ,  H01L27/11 ,  H01L23/528

CPC分类号： G11C11/419 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/413 ,  G11C11/418 ,  H01L23/528 ,  H01L27/1104 ,  H01L27/1116

摘要： Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

公开(公告)号：US10318696B1

公开(公告)日：2019-06-11

申请号：US15149249

申请日：2016-05-09

申请人： Ampere Computing LLC

发明人： Alfred Yeung ,  Subbayyan Venkatesan ,  Vamsi Srikantam ,  Manoj Kulkarni ,  Ojas Dharia

IPC分类号： G06F17/50

摘要： Techniques efficiently improve circuit design to reduce its sensitivity to random device variation. A characterizer component can identify a subset of cells for an integrated circuit that can be representative of respective other cells of a set of cells. The characterizer component can analyze the representative cells of the subset to generate a variation profile, and can map the representative cells to physical cells used in the design of the circuit. A cell library comprising cells that are usable, have limited usage, and/or have general usage can be generated based on analysis results from the mapped cells. The circuit can be reconstructed based on the list of available cells using the cell library. The reconstructed circuit can be analyzed, and in case of a cell(s) violating a constraint, the cell(s) can be modified or enhanced to achieve target performance criteria.

公开(公告)号：US10162373B1

公开(公告)日：2018-12-25

申请号：US15444478

申请日：2017-02-28

申请人： Ampere Computing LLC

发明人： Yan Chong ,  Luca Ravezzi ,  Alfred Yeung ,  Hamid Partovi

IPC分类号： G05F1/56 ,  G01R19/00 ,  H03L7/00 ,  H03K5/24 ,  G01R19/165

摘要： Various aspects provide for detecting voltage droops. For example, a system can include a voltage calibrator component and a comparator component. The voltage calibrator component can convert a first supply voltage associated with a power distribution network of an integrated circuit to a second supply voltage via a resistance ladder circuit. The comparator component can generate a comparison output signal in response to a determination that a comparison between the second supply voltage and a reference voltage satisfies a defined criterion.

公开(公告)号：US10049725B2

公开(公告)日：2018-08-14

申请号：US15372581

申请日：2016-12-08

申请人： Ampere Computing LLC

发明人： Russell Homer ,  Abhiram Saligram Chandrashekar ,  Alfred Yeung

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  H01L27/11 ,  H01L23/528

CPC分类号： G11C11/419 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/413 ,  G11C11/418 ,  H01L27/1104 ,  H01L27/1116

摘要： Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.

公开(公告)号：US20180210987A1

公开(公告)日：2018-07-26

申请号：US15414739

申请日：2017-01-25

申请人： Ampere Computing LLC

发明人： Alfred Yeung ,  Subbayyan Venkatsan ,  Hamid Partovi ,  Vamsi Srikantam

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F17/5081

摘要： Techniques efficiently improve an integrated circuit design by simultaneously analyzing timing paths of the circuit design. A design management component can access data relating to the integrated circuit design from a design database. The design management component can perform a static timing analysis of the integrated circuit design and generate a timing path distribution, filtered analytics, and/or a probability density function associated with the integrated circuit design, wherein all of the timing paths of the integrated circuit design can be evaluated. The design management component can determine a modification to make to a cell, device, interconnection between cells or devices, or another element(s) of the integrated circuit design, based at least in part on the static timing analysis, the timing path distribution, the filtered analytics, and/or the probability density function, to generate a modified integrated circuit design, in accordance with defined design criteria.

公开(公告)号：US10348281B1

公开(公告)日：2019-07-09

申请号：US15256787

申请日：2016-09-06

申请人： Ampere Computing LLC

发明人： David S. Oliver ,  Matthew W. Ashcraft ,  Luca Ravezzi ,  Alfred Yeung ,  John Gregory Favor

IPC分类号： G06F1/00 ,  H03K5/1252 ,  H03L7/00

摘要： Various aspects provide for mitigating voltage droop associated with a microprocessor (e.g., by controlling a clock associated with the microprocessor). For example, a system can include a microprocessor and a controller. The microprocessor can receive a clock provided by a clock buffer. The controller can control frequency of the clock provided by the clock buffer based on a voltage associated with the microprocessor. In an aspect, the controller can reduce the frequency of the clock in response to a determination that the voltage satisfies a defined criterion. Additionally, the controller can incrementally increase the frequency of the clock in response to another determination that the voltage satisfies another defined criterion after satisfying the defined criterion.

公开(公告)号：US10109345B2

公开(公告)日：2018-10-23

申请号：US15980169

申请日：2018-05-15

申请人： AMPERE COMPUTING LLC

发明人： Russell Homer ,  Abhiram Saligram Chandrashekar ,  Alfred Yeung

IPC分类号： G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  H01L23/528 ,  G11C11/418

摘要： Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.