- Patent Title: Memory compression operable for non-contiguous write/read addresses
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Application No.: US15895721Application Date: 2018-02-13
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Publication No.: US10320412B2Publication Date: 2019-06-11
- Inventor: Sundarrajan Rangachari , Desmond Pravin Martin Fernandes , Rakesh Channabasappa Yaraduyathinahalli
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Kenneth Liu; Charles A. Brill; Frank D. Cimino
- Priority: IN5194/CHE/2014 20141017
- Main IPC: G06F3/06
- IPC: G06F3/06 ; H03M7/30 ; G06F13/00

Abstract:
Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.
Public/Granted literature
- US20180175880A1 MEMORY COMPRESSION OPERABLE FOR NON-CONTIGUOUS WRITE/READ ADDRESSES Public/Granted day:2018-06-21
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