Invention Grant
- Patent Title: Method for performing random read access to a block of data using parallel LUT read instruction in vector processors
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Application No.: US15991653Application Date: 2018-05-29
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Publication No.: US10331347B2Publication Date: 2019-06-25
- Inventor: Jayasree Sankaranarayanan , Dipan Kumar Mandal
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Kenneth Liu; Charles A. Brill; Frank D. Cimino
- Priority: IN5509/CHE/2014 20141103
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F9/30 ; G06F9/38

Abstract:
This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
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