Invention Grant
- Patent Title: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption
-
Application No.: US15711110Application Date: 2017-09-21
-
Publication No.: US10332590B2Publication Date: 2019-06-25
- Inventor: Xia Li , Jianguo Yao
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: W&T/Qualcomm
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C11/4094 ; G11C11/4091 ; G11C11/4074 ; G11C7/10 ; G11C11/412 ; G11C11/56 ; G11C8/16

Abstract:
Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.
Public/Granted literature
Information query
IPC分类: