Invention Grant
- Patent Title: Method of manufacturing an electronics package using device-last or device-almost last placement
-
Application No.: US15670423Application Date: 2017-08-07
-
Publication No.: US10332832B2Publication Date: 2019-06-25
- Inventor: Christopher James Kapusta , Raymond Albert Fillion , Risto Ilkka Sakari Tuominen , Kaustubh Ravindra Nagarkar
- Applicant: General Electric Company
- Applicant Address: US NY Schenectady
- Assignee: General Electric Company
- Current Assignee: General Electric Company
- Current Assignee Address: US NY Schenectady
- Agency: Ziolkowski Patent Solutions Group, SC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/522 ; H01L23/495 ; H01L25/04 ; H01L23/00 ; H01L21/48

Abstract:
A method of manufacturing a multi-layer electronics package includes attaching a base insulating substrate to a frame having an opening therein and such that the frame is positioned above and/or below the base insulating substrate to provide support thereto. A first conductive wiring layer is applied on the first side of the base insulating substrate, and vias are formed in the base insulating substrate. A second conductive wiring layer is formed on the second side of the base insulating substrate that covers the vias and the exposed portions of the first conductive wiring layer and at least one additional insulating substrate is bonded to the base insulating substrate. Vias are formed in each additional insulating substrate and an additional conductive wiring layer is formed on each of the additional insulating substrate. The described build-up forms a multilayer interconnect structure, with the frame providing support for this build-up.
Public/Granted literature
- US20190043802A1 METHOD OF MANUFACTURING AN ELECTRONICS PACKAGE USING DEVICE-LAST OR DEVICE-ALMOST LAST PLACEMENT Public/Granted day:2019-02-07
Information query
IPC分类: