Invention Grant
- Patent Title: Method for manufacturing horizontal-gate-all-around devices with different number of nanowires
-
Application No.: US15194807Application Date: 2016-06-28
-
Publication No.: US10332970B2Publication Date: 2019-06-25
- Inventor: Georgios Vellianitis , Gerben Doornbos
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L29/423 ; H01L29/66 ; H01L29/06 ; H01L29/775 ; H01L29/786 ; B82Y10/00 ; H01L21/8234 ; H01L29/10

Abstract:
A method includes the following operations: (i) receiving a FET precursor including a first fin and a second fin, each of the first fin and the second fin having nanowire channels and sacrificial layers; (ii) forming a dummy gate traversing the first and second fins, thereby defining channel regions of the first and second fins under the dummy gate; (iii) forming source/drain features from exposed portions of the first and second fins; (iv) removing the dummy gate to expose the channel regions of the first and second fins; and (v) suspending the nanowire channels of the first and second fins by removing portions of the sacrificial layers of the first and second fins.
Public/Granted literature
- US20170373163A1 METHOD FOR MANUFACTURING HORIZONTAL-GATE-ALL-AROUND DEVICES WITH DIFFERENT NUMBER OF NANOWIRES Public/Granted day:2017-12-28
Information query
IPC分类: