Invention Grant
- Patent Title: Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same
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Application No.: US15553910Application Date: 2016-02-25
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Publication No.: US10333553B2Publication Date: 2019-06-25
- Inventor: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
- Applicant: Electronics and Telecommunications Research Institute
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: NSIP Law
- Priority: KR10-2015-0028064 20150227; KR10-2016-0020854 20160222
- International Application: PCT/KR2016/001878 WO 20160225
- International Announcement: WO2016/137254 WO 20160901
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/15 ; H03M13/11 ; H03M13/27 ; H03M13/25 ; H03M13/29
Abstract:
A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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