Invention Grant
- Patent Title: Erase-verify method for three-dimensional memories and memory system
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Application No.: US15803986Application Date: 2017-11-06
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Publication No.: US10340017B2Publication Date: 2019-07-02
- Inventor: Shaw-Hung Ku , Yu-Hung Huang , Cheng-Hsien Cheng , Chih-Wei Lee , Atsuhiro Suzuki , Wen-Jer Tsai
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34 ; G11C16/16 ; G11C8/14

Abstract:
An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
Public/Granted literature
- US20190139615A1 ERASE-VERIFY METHOD FOR THREE-DIMENSIONAL MEMORIES AND MEMORY SYSTEM Public/Granted day:2019-05-09
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