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公开(公告)号：US20240365565A1
公开(公告)日：2024-10-31
申请号：US18306289
申请日：2023-04-25
发明人： Erh-Kun LAI , Feng-Min LEE
CPC分类号： H10B63/34 , H10B61/22 , H10B63/845
摘要： A memory device and a method for manufacturing the same are provided. The memory device includes drain pillar structures, source pillar structures, memory structures surrounding the drain pillar structures respectively, a channel structure, and a gate structure surrounding the drain pillar structures, the source pillar structures and the channel structure. The channel structure is divided into arc channel parts by the drain pillar structures and the source pillar structures.
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2.发明公开公开(公告)号：US20240363164A1
公开(公告)日：2024-10-31
申请号：US18765452
申请日：2024-07-08
发明人： Po-Hao TSENG , Feng-Min LEE , Ming-Hsiu Lee
CPC分类号： G11C15/046 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
摘要： The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.
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公开(公告)号：US12131787B2
公开(公告)日：2024-10-29
申请号：US17891589
申请日：2022-08-19
发明人： Shuo-Nan Hung , E-Yuan Chang , Ji-Yu Hung
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/24 , H03K19/20
摘要： A memory such as a 3D NAND array, having a page buffer having page buffer cells coupled to bit lines has a search word input such as a search word buffer coupled to word lines. A circuit, such as string select gates, is provided to connect a selected set of memory cells in the array to the page buffer. The page buffer includes sensing circuitry configured to apply a match sense signal to a latch in a plurality of storage elements for a stored data word and an input search word. Logic circuitry uses storage elements in the plurality of storage elements of the page buffer to accumulate the match sense signals output by the sensing circuitry over a sequence matching a plurality stored data words to one or more input search words. A match for a search is based on a threshold and the accumulated match sense signals.
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公开(公告)号：US20240355387A1
公开(公告)日：2024-10-24
申请号：US18303726
申请日：2023-04-20
发明人： Yu-Yu LIN , Feng-Min LEE
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C13/0061
摘要： An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
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公开(公告)号：US12114514B2
公开(公告)日：2024-10-08
申请号：US18519230
申请日：2023-11-27
发明人： Feng-Min Lee , Erh-Kun Lai , Dai-Ying Lee , Yu-Hsuan Lin , Po-Hao Tseng , Ming-Hsiu Lee
CPC分类号： H10B63/845 , H10B61/22 , H10B63/34 , H10N50/01 , H10N70/066
摘要： A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.
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公开(公告)号：US20240324199A1
公开(公告)日：2024-09-26
申请号：US18186961
申请日：2023-03-21
发明人： Min-Feng Hung
摘要： A memory device includes a stacked structure, a channel pillar, a plurality of conductive pillars, and a slit. The stacked structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The channel pillar extends through the stacked structure. The plurality of conductive pillars are located in the channel pillar and electrically connected with the channel pillar. The charge storage structure is located between the plurality of conductive layers and the channel pillar. The slit is located in the stacked structure. The slit includes a body part and an extension part. The body part extends through the stacked structure. The extension part is connected to the body part and located between the stacked structure and the dielectric substrate. The memory may be applied in 3D AND flash memory.
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公开(公告)号：US12101068B2
公开(公告)日：2024-09-24
申请号：US17349586
申请日：2021-06-16
发明人： Yih-Shan Yang
CPC分类号： H03F3/45632 , H03F3/45174 , H03F3/45273 , H03F3/45484 , H03K3/26 , H03K3/356034
摘要： A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.
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公开(公告)号：US20240304579A1
公开(公告)日：2024-09-12
申请号：US18178580
申请日：2023-03-06
发明人： Dai-Ying LEE , Cheng-Hsien LU
CPC分类号： H01L24/08 , H01L24/03 , H01L24/48 , H01L24/80 , H10B80/00 , H01L2224/03848 , H01L2224/05649 , H01L2224/05657 , H01L2224/05666 , H01L2224/05671 , H01L2224/0568 , H01L2224/05681 , H01L2224/05687 , H01L2224/08112 , H01L2224/08146 , H01L2224/48221 , H01L2224/80895 , H01L2224/80896 , H01L2924/1436 , H01L2924/1438 , H01L2924/1443
摘要： Semiconductor devices and a method for forming a semiconductor device are provided. The semiconductor device includes a substrate, a first semiconductor structure on the substrate, a second semiconductor structure on the first semiconductor structure, and a wire coupled between the substrate and the first semiconductor structure. The first semiconductor structure and the second semiconductor structure are electrically connected to the substrate through the wire. A footprint of the first semiconductor structure is greater than a footprint of the second semiconductor structure.
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公开(公告)号：US12086414B2
公开(公告)日：2024-09-10
申请号：US17961176
申请日：2022-10-06
发明人： Chin-Hung Chang , Ken-Hui Chen , Chun-Hsiung Hung
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0679 , G11C15/04
摘要： Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.
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公开(公告)号：US20240281636A1
公开(公告)日：2024-08-22
申请号：US18112827
申请日：2023-02-22
发明人： I-Ting KUO , Hsiang-Lan LUNG
摘要： A method for storing weight data used to compute node values during inferencing operations conducted by a neural network comprises receiving a neural network definition. The neural network definition defines a neural network having a plurality of layers, each having a plurality of nodes. A set of weights used to compute a neural network inferencing result for each neural network node of the plurality of network nodes in the layer is determined. The set of weights determined for the layer in a page of memory can be stored in a high bandwidth non-volatile memory (NVM), such that any weights used to compute the neural network inference result for each neural network node of the plurality of nodes in the layer are stored together in the page of memory for retrieval together. Weights can be stored in different arrays across multiple memory channels.
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