Invention Grant
- Patent Title: Interconnect formation process using wire trench etch prior to via etch, and related interconnect
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Application No.: US15912975Application Date: 2018-03-06
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Publication No.: US10347528B1Publication Date: 2019-07-09
- Inventor: Sunil K. Singh , Ravi P. Srivastava , Sipeng Gu , Akshey Sehgal
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Anthony Canale
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.
Information query
IPC分类: