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    Interconnect formation process using wire trench etch prior to via etch, and related interconnect
    3.
    发明授权
    Interconnect formation process using wire trench etch prior to via etch, and related interconnect 有权

    公开(公告)号：US10347528B1

    公开(公告)日：2019-07-09

    申请号：US15912975

    申请日：2018-03-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sunil K. Singh ,  Ravi P. Srivastava ,  Sipeng Gu ,  Akshey Sehgal

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.

    Interconnect structure with method of forming the same
    5.
    发明授权
    Interconnect structure with method of forming the same 有权

    公开(公告)号：US10312188B1

    公开(公告)日：2019-06-04

    申请号：US15867894

    申请日：2018-01-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ravi P. Srivastava ,  Sunil K. Singh

    IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: An integrated circuit (IC) structure including an interconnect structure is disclosed. The interconnect structure may include a first etch stop layer (ESL) positioned between an initial via layer and a first metal layer of the interconnect structure. The ESL may be positioned adjacent to and surround a metal wire in the first metal layer. A method of forming an interconnect structure is also disclosed. The method may include forming an opening in a first dielectric layer above a substrate; forming a sacrificial semiconductor material in the opening; forming an ESL on the first dielectric layer and sacrificial semiconductor material; forming a second dielectric layer on the ESL; forming an opening in the second dielectric layer to expose a portion of the ESL; removing the exposed portion of the ESL; removing the sacrificial semiconductor material; and forming a conductive material in the openings to form an interconnect structure.

    SADP method with mandrel undercut spacer portion for mandrel space dimension control
    9.
    发明授权
    SADP method with mandrel undercut spacer portion for mandrel space dimension control 有权

    公开(公告)号：US10395941B1

    公开(公告)日：2019-08-27

    申请号：US16106174

    申请日：2018-08-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ravi P. Srivastava ,  Hsueh-Chung Chen

    IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234

    Abstract: A self-aligned double patterning (SADP) method is disclosed. The method may include forming a mandrel over an underlying layer, and undercutting the mandrel forming an undercut space under opposing sides of the mandrel. A pair of spacers may be formed adjacent the mandrel, each spacer including a vertical spacer portion on each side of the mandrel and an undercut spacer portion extending into the undercut space from the vertical spacer portion, the undercut spacer portions defining a sub-lithographic lateral dimension therebetween. The mandrels may be removed and, a sub-lithographic feature etched into at least the underlying layer using the spacers.

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