Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.