-
公开(公告)号：US20220377352A1
公开(公告)日：2022-11-24
申请号：US17816136
申请日：2022-07-29
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Anthony P. DeLaurier , Karthik Ramani , Stephan Lachowsky
IPC: H04N19/182 , H03M7/30
Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, amounts of data needed to represent, using a given lossless compression technique of the multiple lossless compression techniques, individual pixels in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on comparison, among the compression techniques, of sums of: the determined amount of data for an individual pixel for a given lossless compression technique and compression metadata size for a given lossless compression technique. The compression circuitry may generate and store information that encodes values for the set of pixels using the selected compression technique.
-
公开(公告)号：US11405622B2
公开(公告)日：2022-08-02
申请号：US16855459
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Anthony P. DeLaurier , Karthik Ramani , Stephan Lachowsky
IPC: H04N11/02 , H04N19/182 , H03M7/30
Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, a number of bits needed to represent a least compressible pixel, using that technique, in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on the determined numbers of bits for the multiple compression techniques and corresponding header sizes. In some embodiments, the compression circuitry determines, for multiple regions of pixels in the set of pixels, for ones of the compression techniques, a region number of bits needed to represent a least compressible pixel, using that technique. The selection of a compression technique may be further based on region numbers of bits.
-
公开(公告)号：US20210337218A1
公开(公告)日：2021-10-28
申请号：US16855459
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Anthony P. DeLaurier , Karthik Ramani , Stephan Lachowsky
IPC: H04N19/182 , H03M7/30
Abstract: Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, a number of bits needed to represent a least compressible pixel, using that technique, in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on the determined numbers of bits for the multiple compression techniques and corresponding header sizes. In some embodiments, the compression circuitry determines, for multiple regions of pixels in the set of pixels, for ones of the compression techniques, a region number of bits needed to represent a least compressible pixel, using that technique. The selection of a compression technique may be further based on region numbers of bits.
-
公开(公告)号：US20210074053A1
公开(公告)日：2021-03-11
申请号：US16953021
申请日：2020-11-19
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Michael J. Swift , Michal Valient , Robert S. Hartog , Tyson J. Bergland , Gokhan Avkarogullari
IPC: G06T15/04 , G06T1/60 , G06F9/38 , G06T11/00 , G06F12/1009 , G06F9/50 , G06T15/00 , G06F12/0811
Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.
-
公开(公告)号：US20180349291A1
公开(公告)日：2018-12-06
申请号：US15610008
申请日：2017-05-31
Applicant: Apple Inc.
Inventor： Wolfgang H. Klingauf , Kenneth C. Dyke , Karthik Ramani , Winnie W. Yeung , Anthony P. DeLaurier , Luc R. Semeria , David A. Gotwalt , Srinivasa Rangan Sridharan , Muditha Kanchana
IPC: G06F12/123 , G06F12/0808 , G06F12/0815 , G06F12/0804
CPC classification number: G06F12/123 , G06F12/0804 , G06F12/0808 , G06F12/0815 , G06F2212/608 , G06F2212/621 , G06F2212/69
Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.
-
Patent Agency Ranking
公开(公告)号：US09530237B2
公开(公告)日：2016-12-27
申请号：US14677280
申请日：2015-04-02
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Andrew Pomianowski , Anthony P. DeLaurier
CPC classification number: G06T15/04 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/12
Abstract: Techniques are disclosed relating to interpolation for texture mapping. In some embodiments, a graphics unit includes circuitry configured to map a texture to a screen space such that a set of multiple in the screen space falls between first and second adjacent texels of the texture in a first dimension. In some embodiments, the graphics unit also includes texture processing circuitry configured to perform different types of interpolation for pixels in the group of pixels. In these embodiments, this includes determining pixel attributes for first and second end groups of pixels in the set of pixels using a nearest-neighbor interpolation technique and attributes of the first and second texels respectively. In these embodiments, this also includes determining pixel attributes for an intermediate group of pixels in the set of pixels using a second, different interpolation technique and attributes of both the first and second texels.
Abstract translation: 公开了关于纹理映射的插值的技术。 在一些实施例中，图形单元包括被配置为将纹理映射到屏幕空间的电路，使得屏幕空间中的多个集合在第一维度中落在纹理的第一和第二相邻纹素之间。 在一些实施例中，图形单元还包括纹理处理电路，其被配置为对像素组中的像素执行不同类型的内插。 在这些实施例中，这包括使用最近邻内插技术和第一和第二纹素的属性来确定像素集合中的像素的第一和第二端组的像素属性。 在这些实施例中，这还包括使用第二不同的插值技术和第一和第二纹素两者的属性来确定像素集合中的中间像素组的像素属性。
-
公开(公告)号：US11062507B2
公开(公告)日：2021-07-13
申请号：US16673883
申请日：2019-11-04
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Karl D. Mann , Tyson J. Bergland , Winnie W. Yeung
Abstract: Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.
-
公开(公告)号：US10970223B2
公开(公告)日：2021-04-06
申请号：US16410828
申请日：2019-05-13
Applicant: Apple Inc.
Inventor： Wolfgang H. Klingauf , Kenneth C. Dyke , Karthik Ramani , Winnie W. Yeung , Anthony P. DeLaurier , Luc R. Semeria , David A. Gotwalt , Srinivasa Rangan Sridharan , Muditha Kanchana
IPC: G06F12/08 , G06F12/0891 , G06F12/0804 , G06F12/0808 , G06F12/0815 , G06F12/123 , G06F12/0895 , G06F12/126 , G06F12/12
Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.
-
公开(公告)号：US10354431B2
公开(公告)日：2019-07-16
申请号：US14735707
申请日：2015-06-10
Applicant: Apple Inc.
Inventor： Abdulkadir U. Diril , Adam T. Moerschell , Anthony P. DeLaurier
Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.
-
公开(公告)号：US10324844B2
公开(公告)日：2019-06-18
申请号：US15389047
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Anthony P. DeLaurier , Owen C. Anderson , Michael J. Swift , Aaftab A. Munshi , Terence M. Potter
IPC: G09G5/36 , G06F12/0815 , G06F12/0811 , G06F12/084 , G06T1/60
Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.026 seconds)
