- Patent Title: Techniques associated with server transaction latency information
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Application No.: US15357415Application Date: 2016-11-21
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Publication No.: US10355959B2Publication Date: 2019-07-16
- Inventor: Manasi Deval , Jim Daubert , Eric K. Mann , Cong Li , Muralidhar Murali Rajappa , Anjaneya Reddy Chagam Reddy , David Wescott , Ramkumar Nagappan , Raed Kanjo
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/26 ; H04L29/08 ; H04L1/16 ; H04L12/24 ; H04L12/851 ; H04L12/931 ; H04L29/06

Abstract:
Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may be capable of time stamping information related to ingress request and egress response packets for a transaction. For these examples, elements of the server may be capable of determining transaction latency values based on the time stamped information. The determined transaction latency values may be used to monitor or manage operating characteristics of the server to include an amount of power provided to the server or an ability of the server to support one or more virtual servers. Other examples are described and claimed.
Public/Granted literature
- US20170201448A1 Techniques Associated with Server Transaction Latency Information Public/Granted day:2017-07-13
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