Managing a power state of a processor
    1.
    发明授权
    Managing a power state of a processor 有权
    管理处理器的电源状态

    公开(公告)号:US09372526B2

    公开(公告)日:2016-06-21

    申请号:US13724594

    申请日:2012-12-21

    Abstract: A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.

    Abstract translation: 本文描述了用于管理处理器的电源状态的方法和系统。 该方法包括在处理器处接收指示要向处理器发送中断的信号。 该方法还包括响应于接收到信号并将处理器从浅空闲状态转换到活动状态以响应于接收到中断而将处理器从深空闲状态转换到浅空闲状态。

    Efficient QoS support for software packet processing on general purpose servers

    公开(公告)号:US10237171B2

    公开(公告)日:2019-03-19

    申请号:US15270377

    申请日:2016-09-20

    Abstract: Methods and apparatus for facilitating efficient Quality of Service (QoS) support for software-based packet processing by offloading QoS rate-limiting to NIC hardware. Software-based packet processing is performed on packet flows received at a compute platform, such as a general purpose server, and/or packet flows generated by local applications running on the compute platform. The packet processing includes packet classification that associates packets with packet flows using flow IDs, and identifying a QoS class for the packet and packet flow. NIC Tx queues are dynamically configured or pre-configured to effect rate limiting for forwarding packets enqueued in the NIC Tx queues. New packet flows are detected, and mapping data is created to map flow IDs associated with flows to the NIC Tx queues used to forward the packets associated with the flows.

    Intelligent receive buffer management to optimize idle state residency
    4.
    发明授权
    Intelligent receive buffer management to optimize idle state residency 有权
    智能接收缓冲区管理,优化空闲状态驻留

    公开(公告)号:US09223379B2

    公开(公告)日:2015-12-29

    申请号:US13728355

    申请日:2012-12-27

    CPC classification number: G06F1/3234 Y02D50/20

    Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.

    Abstract translation: 方法和系统可以提供用于确定对应的多个空闲状态的多个缓冲器相关设置,并将多个缓冲器相关设置输出到平台上的设备。 设备可以确定与接收缓冲器相关联的通道的观察带宽,并且至少部分地基于观察到的带宽来识别来自多个缓冲器相关设置的与缓冲器相关的设置的选择。 在一个示例中,每个与缓冲器相关的设置包括延迟容限和相应的空闲持续时间。

Patent Agency Ranking