Invention Grant
- Patent Title: Buffer circuit for enhancing bandwidth of voltage regulator and voltage regulator using the same
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Application No.: US16221608Application Date: 2018-12-17
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Publication No.: US10359796B1Publication Date: 2019-07-23
- Inventor: Jie-Yu Liao , Chun-Hung Chen , Hsueh-Yi Lee
- Applicant: NOVATEK Microelectronics Corp.
- Applicant Address: TW Hsin-Chu
- Assignee: NOVATEK Microelectronics Corp.
- Current Assignee: NOVATEK Microelectronics Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G05F1/563
- IPC: G05F1/563 ; G05F1/63 ; G05F1/575 ; H03F1/30 ; H02M1/15
Abstract:
A buffer circuit includes a first transistor, a second transistor, a feed-forward circuit and a resistive bias circuit. The first transistor has a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is served as an input terminal of the buffer circuit. The second transistor has a first terminal and a second terminal, wherein the second terminal of the second transistor is coupled to the third terminal of the first transistor and served as an output terminal of the buffer circuit. The feed-forward circuit has a first terminal and a second terminal respectively coupled to the first terminal of the second transistor and the second terminal of the first transistor. The resistive bias circuit has a first terminal and a second terminal respectively coupled to the second terminal of the first transistor and the first terminal of the feed-forward circuit.
Information query
IPC分类:
