Invention Grant
- Patent Title: Biasing current regularization loop stabilization
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Application No.: US15693214Application Date: 2017-08-31
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Publication No.: US10359800B2Publication Date: 2019-07-23
- Inventor: Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
- Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS
- Applicant Address: FR Grenoble FR Grenoble
- Assignee: STMicroelectronics (Grenoble 2) SAS,STMicroelectronics (Alps) SAS
- Current Assignee: STMicroelectronics (Grenoble 2) SAS,STMicroelectronics (Alps) SAS
- Current Assignee Address: FR Grenoble FR Grenoble
- Agency: Slater Matsil, LLP
- Priority: FR1751294 20170217
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02 ; G05F3/26 ; H03F3/195 ; G05F1/46 ; H03F3/16

Abstract:
An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
Public/Granted literature
- US20180239384A1 BIASING CURRENT REGULARIZATION LOOP STABILIZATION Public/Granted day:2018-08-23
Information query
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