A module circuit (11) comprises a sensor terminal (43) for feeding a sensor signal (SP) and a clock terminal (41) for feeding a pulse width-modulated clock signal (ST) having a first and a second clock phase (A, B). A signal processing circuit (40) of the module circuit (11) is coupled on the input side to the sensor terminal (43) and the clock terminal (41) and is designed to provide an output signal (SAL) dependent on the sensor signal (SP) that can be tapped in the first clock phase (A) and independent of the sensor signal (SP) that can be tapped in the second clock phase (B).