Invention Grant
- Patent Title: Vertical channel transistors fabrication process by selective subtraction of a regular grid
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Application No.: US15120720Application Date: 2014-09-24
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Publication No.: US10361090B2Publication Date: 2019-07-23
- Inventor: Kimin Jun , Patrick Morrow , Donald Nelson
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2014/057257 WO 20140924
- International Announcement: WO2015/191096 WO 20151217
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L29/66 ; H01L29/78 ; H01L21/768 ; H01L29/06

Abstract:
A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.
Public/Granted literature
- US20170011929A1 VERTICAL CHANNEL TRANSISTORS FABRICATION PROCESS BY SELECTIVE SUBTRACTION OF A REGULAR GRID Public/Granted day:2017-01-12
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