Invention Grant
- Patent Title: Methods used in forming an array of elevationally-extending transistors
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Application No.: US15710432Application Date: 2017-09-20
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Publication No.: US10361216B2Publication Date: 2019-07-23
- Inventor: Jordan D. Greenlee , John Mark Meldrim , E. Allen McTeer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11556

Abstract:
A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.
Public/Granted literature
- US20190088671A1 Methods Used In Forming An Array Of Elevationally-Extending Transistors Public/Granted day:2019-03-21
Information query
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