Invention Grant
- Patent Title: Instructions for managing a parallel cache hierarchy
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Application No.: US15583258Application Date: 2017-05-01
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Publication No.: US10365930B2Publication Date: 2019-07-30
- Inventor: John R. Nickolls , Brett W. Coon , Michael C. Shebanow
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28 ; G06F9/38 ; G06F12/0811 ; G06F12/0862 ; G06F12/121 ; G06F9/30 ; G06F12/0875 ; G06F12/0897 ; G06F12/0871

Abstract:
A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.
Public/Granted literature
- US20170235581A1 INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY Public/Granted day:2017-08-17
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