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    PADDING IN A STREAM OF MATRIX ELEMENTS
    2.
    发明申请
    PADDING IN A STREAM OF MATRIX ELEMENTS 有权

    公开(公告)号：US20250036411A1

    公开(公告)日：2025-01-30

    申请号：US18914395

    申请日：2024-10-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Son Hung Tran ,  Shyam Jagannathan ,  Timothy David Anderson

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F15/80 ,  G06F17/16

    Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a specified width for a selected dimension of the array. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. When the selected dimension in the stream of vectors exceeds the specified width, the streaming engine inserts null elements into each portion of a respective vector for the selected dimension that exceeds the specified width in the stream of vectors. Stream vectors that are completely null are formed by the streaming engine without accessing the system memory for respective data.

    CACHE LOOK UP DURING PACKET PROCESSING BY UNIFORMLY CACHING NON-UNIFORM LENGTHS OF PAYLOAD DATA IN A DUAL-STAGE CACHE OF PACKET PROCESSORS
    6.
    发明申请
    CACHE LOOK UP DURING PACKET PROCESSING BY UNIFORMLY CACHING NON-UNIFORM LENGTHS OF PAYLOAD DATA IN A DUAL-STAGE CACHE OF PACKET PROCESSORS 有权

    公开(公告)号：US20240427706A1

    公开(公告)日：2024-12-26

    申请号：US18754158

    申请日：2024-06-26

    Applicant: Fortinet, Inc.

    Inventor： Shushan Wen ,  Zhi Guo

    IPC: G06F12/0897

    Abstract: At a first stage, cells of a row of the index table are searched, using a portion of the unified hash value bits as index to identify the row of the index table. Also, a pointer to the content table is identified by comparing an index table tag of an entry of a cell with a calculated tag of the hash to identify a cell in the row. At a second stage, a cell is looked up in the content table, responsive to a match of calculated tag of the hash and index table tag of entry, comparing the current full key value and the full key value in the content table entry. The content table full key value is retrieved using a pointer from the cell of the index table to the content table from the cell entry.

    CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
    9.
    发明申请
    CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS 有权

    公开(公告)号：US20240419324A1

    公开(公告)日：2024-12-19

    申请号：US18822571

    申请日：2024-09-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Matthew Pierson

    IPC: G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/14

    Abstract: Disclosed embodiments relate to one or more techniques to control access by a requestor of a computing system to a shared memory resource. In one embodiment, a technique includes determining a number (N) of pending requests to be sent to the memory by the requestor, determining a number (M) of requests that the requestor is limited to sending based on an amount of buffering resources available, and comparing M to N. When N is both greater than zero and less than or equal to M, the requestor sends the N pending requests to the memory. When N is both greater than zero and greater than M, M is compared to a hysteresis value (R) and, when M is less than R, the requestor sends R of the N pending requests to the memory.

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