A computing apparatus, including at least one general computing core circuit, an internal interface circuit, an external interface circuit, a cache coherence engine circuit, and a protocol conversion circuit. The computing apparatus is coupled to an internal apparatus using the internal interface circuit, and is coupled to an external apparatus using the external interface circuit. When working in a first mode, the cache coherence engine circuit implements cache coherence between the computing apparatus, the internal apparatus, and the external apparatus, and in this case, the computing apparatus is used as a node controller. When working in a second mode, the cache coherence engine circuit processes only cache coherence between the computing apparatus and the internal apparatus, and the external interface circuit is used as a network interface circuit.