Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.