Invention Grant
- Patent Title: Semiconductor memory devices including separate upper and lower bit line spacers
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Application No.: US15845141Application Date: 2017-12-18
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Publication No.: US10373960B2Publication Date: 2019-08-06
- Inventor: Daeik Kim , Semyeong Jang , Jemin Park , Yoosang Hwang
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR10-2017-0043124 20170403
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/71 ; H01L27/108 ; H01L29/792 ; H01L21/8234
Abstract:
A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
Public/Granted literature
- US20180286870A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATE UPPER AND LOWER BIT LINE SPACERS Public/Granted day:2018-10-04
Information query
IPC分类:
