A timing device includes a counter that performs counting action in synchronization with pulses in a clock signal to generate a 6-bit count value representing decimal numbers “0” to “39” in each count cycle in order to perform counting action on a 1/100-second basis and an output control circuit that outputs upper 4 bits of the count value generated by the counter as 4-bit timed data representing time on a 1/1000-second basis.