公开(公告)号：US10379571B2

公开(公告)日：2019-08-13

申请号：US15355504

申请日：2016-11-18

Applicant: Seiko Epson Corporation

Inventor： Masayuki Kamiyama ,  Tsuyoshi Yoneyama ,  Toru Shirotori

IPC: G06F1/12

Abstract: A timing device includes a counter that performs counting action in synchronization with pulses in a clock signal to generate a 6-bit count value representing decimal numbers “0” to “39” in each count cycle in order to perform counting action on a 1/100-second basis and an output control circuit that outputs upper 4 bits of the count value generated by the counter as 4-bit timed data representing time on a 1/1000-second basis.

公开(公告)号：US09075396B2

公开(公告)日：2015-07-07

申请号：US13690623

申请日：2012-11-30

Applicant: SEIKO EPSON CORPORATION

Inventor： Makoto Takemura ,  Toru Shirotori

IPC: G04F1/00 ,  G06F1/08 ,  G04F3/06

CPC classification number: G04F1/005 ,  G04F3/06 ,  G06F1/08

Abstract: A timer device includes a RES input terminal (first external terminal), an input time determination circuit that determines the time length relationship between an input time of a predetermined signal input to the RES input terminal and a given determination time, and a pre-settable down counter (counting circuit) that counts a given set value. The pre-settable down counter changes a process according to a determination result of the input time determination circuit.

Abstract translation: 定时器装置包括RES输入端（第一外部端子），输入时间确定电路，确定输入到RES输入端的预定信号的输入时间与给定的确定时间之间的时间长度关系，以及可预设的 递减计数器（计数电路），计数给定的设定值。 可预置的下计数器根据输入时间确定电路的确定结果改变处理。

公开(公告)号：US10128854B2

公开(公告)日：2018-11-13

申请号：US15245774

申请日：2016-08-24

Applicant: Seiko Epson Corporation

Inventor： Toru Shirotori ,  Hisashi Yamaguchi ,  Masaki Wakamori ,  Toshiya Usuda ,  Sho Matsuzaki ,  Tsuyoshi Yoneyama ,  Masayuki Kamiyama ,  Hiroshi Kiya

IPC: H03L1/04 ,  H03B5/32 ,  H03L1/02 ,  H03B5/12

Abstract: An oscillation circuit includes an oscillating circuit adapted to oscillate a resonator element having a frequency-temperature characteristic, and a frequency adjustment circuit having a capacitance circuit connected to the oscillating circuit and adapted to adjust an oscillation frequency of the oscillating circuit, and a logic circuit, to which a signal having been output from the oscillating circuit is input, and which adjusts a frequency of the signal, and the frequency adjustment circuit compensates the frequency-temperature characteristic using at least the capacitance circuit in a predetermined temperature range, and compensates the frequency-temperature characteristic using the logic circuit alone outside the predetermined temperature range.

公开(公告)号：US08824623B2

公开(公告)日：2014-09-02

申请号：US13691182

申请日：2012-11-30

Applicant: Seiko Epson Corporation

Inventor： Makoto Takemura ,  Toru Shirotori

IPC: H03K21/38 ,  G04F3/06 ,  G04F10/00

CPC classification number: G04F10/00 ,  G04F3/06

Abstract: A timer device includes a RES input terminal, an OUT output terminal, a delay circuit that delays a signal input to the RES input terminal, and a pre-settable down counter that counts a given set value, and outputs a measurement completion signal via an output terminal when the counting of the set value is completed. When a predetermined signal is input to an input terminal after an output of the measurement completion signal, the pre-settable down counter completes the output of the measurement completion signal based on a delay signal obtained by the delaying the predetermined signal using the delay circuit.

Abstract translation: 定时器装置包括RES输入端子，OUT输出端子，延迟输入到RES输入端子的信号的延迟电路以及对给定设定值进行计数的可预先设定的递减计数器，并经由 当设定值的计数结束时，输出端子。 当在测量完成信号的输出之后向输入端子输入预定信号时，可预先设定的下降计数器基于通过使用延迟电路延迟预定信号而获得的延迟信号来完成测量完成信号的输出。

公开(公告)号：US10135391B2

公开(公告)日：2018-11-20

申请号：US15245670

申请日：2016-08-24

Applicant: Seiko Epson Corporation

Inventor： Toru Shirotori ,  Hisashi Yamaguchi ,  Masaki Wakamori ,  Toshiya Usuda ,  Masayuki Kamiyama ,  Sho Matsuzaki ,  Hiroshi Kiya ,  Tsuyoshi Yoneyama

IPC: H03L1/04 ,  H03B5/32 ,  H03L1/02 ,  H03B5/04 ,  H03B5/12

Abstract: An oscillation circuit includes an oscillating circuit adapted to oscillate a resonator element, a capacitance circuit connected to the oscillating circuit, and capable of correcting an oscillation frequency of the oscillating circuit, a logic circuit to which a signal output from the oscillating circuit is input, and which is capable of correcting a frequency of the signal, and a control circuit adapted to control an operation of the capacitance circuit and an operation of the logic circuit.