Invention Grant
- Patent Title: Memory apparatus for in-chip error correction
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Application No.: US15470657Application Date: 2017-03-27
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Publication No.: US10379939B2Publication Date: 2019-08-13
- Inventor: Krishna T. Malladi , Hongzhong Zheng
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Lewis Roca Rothgerber Christie LLP
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F21/64 ; G11C29/00 ; G11C29/04 ; G11C29/44

Abstract:
A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected.
Public/Granted literature
- US20180189132A1 MEMORY APPARATUS FOR IN-CHIP ERROR CORRECTION Public/Granted day:2018-07-05
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