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    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL
    3.
    发明申请
    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL 有权

    公开(公告)号：US20230069786A1

    公开(公告)日：2023-03-02

    申请号：US18045332

    申请日：2022-10-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Andrew Chang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/42

    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

    SYSTEM AND METHOD FOR IN-MEMORY COMPUTATION
    4.
    发明申请
    SYSTEM AND METHOD FOR IN-MEMORY COMPUTATION 有权

    公开(公告)号：US20220206917A1

    公开(公告)日：2022-06-30

    申请号：US17699679

    申请日：2022-03-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Wenqin Huangfu

    IPC: G06F11/30 ,  G06F11/34

    Abstract: A method for computing. In some embodiments, the method includes: calculating an advantage score of a first computing task, the advantage score being a measure of an extent to which a plurality of function in memory circuits is capable of executing the first computing task more efficiently by than one or more extra-memory processing circuits, the first computing task including instructions and data; in response to determining that the advantage score of the first computing task is less than a first threshold, executing the first computing task by the one or more extra-memory processing circuits; and in response to determining that the first computing task is at least equal to the first threshold: compiling the instructions for execution by the function in memory circuits; formatting the data for the function in memory circuits; and executing the first computing task, by the function in memory circuits.

    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL
    6.
    发明申请
    IN-MEMORY COMPUTING WITH CACHE COHERENT PROTOCOL 有权

    公开(公告)号：US20210311739A1

    公开(公告)日：2021-10-07

    申请号：US16914129

    申请日：2020-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Andrew Chang

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/42

    Abstract: A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

    ADJUSTABLE FUNCTION-IN-MEMORY COMPUTATION SYSTEM
    7.
    发明申请
    ADJUSTABLE FUNCTION-IN-MEMORY COMPUTATION SYSTEM 有权

    公开(公告)号：US20210278992A1

    公开(公告)日：2021-09-09

    申请号：US16914151

    申请日：2020-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi

    IPC: G06F3/06

    Abstract: A method for in-memory computing. In some embodiments, the method includes: executing, by a first function-in-memory circuit, a first instruction, to produce, as a result, a first value, wherein a first computing task includes a second computing task and a third computing task, the second computing task including the first instruction; storing, by the first function-in-memory circuit, the first value in a first buffer; reading, by a second function-in- memory circuit, the first value from the first buffer; and executing, by a second function-in- memory circuit, a second instruction, the second instruction using the first value as an argument, the third computing task including the second instruction, wherein: the storing, by the first function-in-memory circuit, of the first value in the first buffer includes directly storing the first value in the first buffer.

    PSEUDO MAIN MEMORY SYSTEM
    8.
    发明申请
    PSEUDO MAIN MEMORY SYSTEM 有权

    公开(公告)号：US20210271594A1

    公开(公告)日：2021-09-02

    申请号：US17322805

    申请日：2021-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/02 ,  G06F13/16

    Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

    Bandwidth boosted stacked memory
    10.
    发明授权
    Bandwidth boosted stacked memory 有权

    公开(公告)号：US10915451B2

    公开(公告)日：2021-02-09

    申请号：US16439613

    申请日：2019-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G06F12/0879 ,  G11C11/417

    Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

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