Invention Grant
- Patent Title: Structure and method for integrated circuits packaging with increased density
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Application No.: US14289483Application Date: 2014-05-28
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Publication No.: US10381326B2Publication Date: 2019-08-13
- Inventor: Charles G. Woychik , Arkalgud R. Sitaram , Andrew Cao , Bong-Sub Lee
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/00 ; H01L21/768 ; H01L21/56 ; H01L23/373 ; H01L23/367 ; H01L23/29 ; H01L23/31 ; H01L23/48 ; H01L21/683 ; H01L25/03 ; H01L25/18

Abstract:
A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.
Public/Granted literature
- US20150348940A1 STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS PACKAGING WITH INCREASED DENSITY Public/Granted day:2015-12-03
Information query
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