Invention Grant
- Patent Title: Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal
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Application No.: US16006192Application Date: 2018-06-12
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Publication No.: US10387048B2Publication Date: 2019-08-20
- Inventor: Eric Lee , Qiang Tang , Ali Feiz Zarrin Ghalam , Hoon Choi , Daesik Song
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/32
- IPC: G11C16/32 ; G06F3/06 ; G11C16/26 ; G06F12/0802 ; G11C7/10 ; G11C7/22 ; G06F12/02
Abstract:
Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.
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