Invention Grant
- Patent Title: Methods and devices using PVD ruthenium
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Application No.: US15718412Application Date: 2017-09-28
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Publication No.: US10388532B2Publication Date: 2019-08-20
- Inventor: Jothilingam Ramalingam , Ross Marshall , Jianxin Lei , Xianmin Tang
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Servilla Whitney LLC
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L29/49 ; H01L21/02 ; H01L29/66 ; H01L21/786 ; H01L29/78 ; C23C14/14 ; C23C14/58 ; C23C14/50 ; C23C14/34 ; H01L21/768 ; C23C14/18 ; C23C14/35 ; H01L21/683

Abstract:
Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.
Public/Granted literature
- US20180096852A1 Methods and Devices Using PVD Ruthenium Public/Granted day:2018-04-05
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