Invention Grant
- Patent Title: Protection from ESD during the manufacturing process of semiconductor chips
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Application No.: US15636533Application Date: 2017-06-28
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Publication No.: US10388594B2Publication Date: 2019-08-20
- Inventor: Frederick Ray Gomez , Tito Mangaoang, Jr. , Jefferson Talledo
- Applicant: STMICROELECTRONICS, INC.
- Applicant Address: PH Calamba
- Assignee: STMICROELECTRONICS, INC.
- Current Assignee: STMICROELECTRONICS, INC.
- Current Assignee Address: PH Calamba
- Agency: Seed IP Law Group LLP
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L21/66 ; H01L23/00 ; H01L23/31 ; H01L23/60 ; H01L23/495

Abstract:
According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.
Public/Granted literature
- US20190006266A1 PROTECTION FROM ESD DURING THE MANUFACTURING PROCESS OF SEMICONDUCTOR CHIPS Public/Granted day:2019-01-03
Information query
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