Invention Grant
- Patent Title: Semiconductor memory system
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Application No.: US15822039Application Date: 2017-11-24
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Publication No.: US10388640B2Publication Date: 2019-08-20
- Inventor: Hayato Masubuchi , Naoki Kimura , Manabu Matsumoto , Toyota Morimoto
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2011-058140 20110316
- Main IPC: G11C5/02
- IPC: G11C5/02 ; H01L25/18 ; H05K1/02 ; H05K3/30 ; H01L23/498 ; H01L27/115 ; H01L23/31 ; H01L23/552 ; H01L23/00 ; H01L25/065 ; H05K1/18 ; H01L23/528 ; H01L25/00

Abstract:
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
Public/Granted literature
- US20180076186A1 SEMICONDUCTOR MEMORY SYSTEM Public/Granted day:2018-03-15
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