Invention Grant
- Patent Title: Semiconductor device with arrangement of semiconductor regions for improving breakdown voltages
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Application No.: US15411987Application Date: 2017-01-21
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Publication No.: US10388741B2Publication Date: 2019-08-20
- Inventor: Takahiro Mori
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2016-034151 20160225
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/40 ; H01L29/66 ; H01L29/78 ; H01L21/265

Abstract:
A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.
Public/Granted literature
- US20170250259A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Public/Granted day:2017-08-31
Information query
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