Invention Grant
- Patent Title: FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming
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Application No.: US15082103Application Date: 2016-03-28
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Publication No.: US10388790B2Publication Date: 2019-08-20
- Inventor: Min-hwa Chi , Ajey Jacob , Abhijeet Paul
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L21/8234 ; H01L29/161 ; H01L21/02 ; H01L21/306 ; H01L21/3065 ; H01L21/308 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L29/16 ; H01L29/165 ; H01L29/66 ; H01L29/10

Abstract:
A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.
Public/Granted literature
- US20160211375A1 FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING Public/Granted day:2016-07-21
Information query
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